Résumé
:
Fabrice Muller a obtenu le titre de Docteur
en électronique de l'Université de
Nantes en 2000, il rejoint l'école d'ingénieurs
Polytech'Nice-Sophia et le
laboratoire I3S en tant que maître de conférences. A
partir de 2007, il intègre
le laboratoire LEAT/CNRS. En décembre 2011, il a obtenu son
H.D.R (Habilitation
à Diriger des Recherches) sur son travail concernant les
architectures
multiprocesseurs, distribuées et reconfigurables dynamiquement
pour les
applications temps réel. Depuis 2018, il est au laboratoire
Polytech'Lab. Il
est actuellement directeur du département d'ingénierie
des systèmes
électroniques à Polytech Nice Sophia et responsable de la
gestion de la qualité
ISO9001:2015. Il se concentre sur la conception conjointe
matérielle/logicielle
et les architectures reconfigurables sur les cibles FPGA, le
placement/partitionnement
des tâches matérielles et l’ordonnancement. Il travaille
également sur des implémentations
de RTOS hardware/software et sur de futures architectures adaptatives.
Il a
participé en tant que co-auteur au logiciel Cofluent Design
créé en 2003,
acquis par Intel en 2011. Depuis 2012, il conçoit actuellement
un outil
FoRTReSS (Flow for Reconfigurable architectures in Real-time System)
pour
l'évaluation de la consommation d'énergie au niveau
système et sur la
génération d'un middleware. Ce middleware permet
d'exécuter et de programmer
des applications modélisées sous l’outil FoRTReSS sur des
architectures
embarquées supportant Linux.
Fabrice
Muller received
the Ph.D. degree in electrical engineering from the University of Nantes in 2000 and he joins the
Polytech'Nice-Sophia engineering school and I3S Laboratory as Associate
Professor. From 2007, he changes for the LEAT/CNRS Laboratory. In
December
2011, he got the H.D.R (Habilitation à Diriger des Recherches)
on his work on
multiprocessor architectures, dynamically distributed and
reconfigurable for
real-time applications. Since 2018, he is at Polytech’Lab. He is
currently
Director of the Department of Electronic Systems Engineering at
Polytech Nice
Sophia and in charge of the quality management ISO9001:2015. He focuses
on
co-design and reconfigurable architectures on FPGA targets, hardware
task
placement/partitioning and scheduling. He also works on implementations
of
hardware/software RTOS and on future adaptive architectures. He was
involved as
co-author in the software Cofluent Design created in 2003, acquired by
Intel in
2011. Since 2012, he currently designs a FoRTReSS tool box (Flow for
Reconfigurable archiTectures in Real-time SystemS) for the evaluation
of the
energy consumption at system level and on the generation of a
middleware which
makes it possible to execute and schedule applications modeled under
FoRTReSS
on embedded architectures supporting Linux.
Domaine d'activité :
Architectures
reconfigurables, FPGA, RTOS, Modélisation
& Simulation de niveau système
Publications :
Ouvrages ou Chapitres de livre :
I.
Belaid, F. Muller & M. Benjemaa, “A
new Three-level strategy for off-line placement of hardware tasks on
partially and dynamically reconfigurable hardware”,
Ed. G. Cogniat, D.
Milojevic, A. Morawiec & A. Erdogan, "Algorithm-Architecture
matching fir
signal and image processing”,
Vol. 73, Lectures Notes in Electrical Engineering, Springer, pp.
145-169, 2011.
Revues
internationales :
F.
Duhem, F. Muller, R. Bonamy & S. Bilavarn, “Fortress: a flow for
design space exploration of partially reconfigurable systems”,
Design
Automation for Embedded Systems, Springer
Verlag 19(3), pp. 301-326, 2015.
F.
Duhem, F. Muller, W. Aubry, B. Le Gal, D. Negru & P.. Lorenzini,
“Design space exploration for partially reconfigurable architectures in
real-time systems”,
Journal
of Systems Architecture, Vol.
59, n° 8, pp. 571-581, 2013.
I.
Belaid, B. Ouni, F. Muller & M. Benjemaa, “Complete
and approximative methods for off-line placement of hardware tasks on
reconfigurable devices”,
Journal
of Circuits, Systems and Computers, Vol.
22, n° 2, 30 p., 2013.
F.
Duhem, N. Marques, F. Muller, H. Rabah, S. Weber & P.. Lorenzini,
“Dynamically reconfigurable architectures entropy coder for
multi-standard video adaptation using farm”,
Microprocessors
and Microsystems, Vol.
37, n° 8, pp. 571-581, 2013.
C. Foucher, F. Muller
& A. Giulieri, “Online codesign on reconfigurble platform for
parallel computing”, Microprocessors and
Microsystems, vol. 37, Issues 4-5, pp. 482-493, 2013.
F. Duhem, F. Muller
& P. Lorenzini, “Reconfiguration time overhead on Field
Programmable Gate arrays: Reduction and cost model”, IET Computers
&
Digital Techniques, vol. 6, n°2, pp. 105-113, 2012.
F. Duhem, N. Marques, F. Muller, H. Rabah, S. Weber
& P. Lorenzini, “Dynamically reconfigurable entropy coder for
multi-standrad video adaptation using FaRM”, Microprocessors and
Microsystems, vol. 37, Issue 1, pp. 1-8, 2013.
I.
Belaid, F. Muller & M. Benjemaa, “Static
scheduling of periodic hardware tasks with precedence and deadline
constraints on reconfigurable hardware devices”,
Special
Issue on ReCoSoC'2010 International Journalof Reconfigurale Computing, Vol.
2011, Article n° 9, 2011.
I.
Belaid, F. Muller & M. Benjemaa, “New
Three-level resource management enhancing quality of off-line hardware
tasks placement on FPGA”,
International
Journalof Reconfigurale Computing, Vol.
2010, Article n° 4, 2010.
F.
Muller, J. Le Rhun, F. Lemonnier, B. Miramond & L. Deveaux, “A
flexible operating system for dynamic applications”,
Xcell
Journal, Issue
73,pp. 30-34,
2010.
Conférences
internationales :
R. Bonamy, S. Bilavarn &
F. Muller, “An energy-aware scheduler for dynamically reconfigurable
multi-core systems”, ReCoSoC, Bremen,
Germany, 2015.
S. Bilavarn, F. Muller
& R. Bonamy, “Heterogeneous power
strategies for reconfigurable many-core architectutres”, European Nanoelectronics Forum, Cannes,
France, 2014.
C. Foucher, F. Muller & A.
Giulieri, “Fast integration of hardware accelerators for dynamically
reconfigurable architecture”, ReCoSoC,
York, UK, 2012.
F. Duhem, F. Muller
& P. Lorenzini, “Methodology for designing partially reconfigurable
systems using transaction-level modeling”, DASIP, Tampere,
Finland, 2011.
I.
Belaid, F. Muller & M. Benjemaa, “Schedulers-driven
approach for dynamic placement/scheduling of multiple dags onto sopcs”,
RSP, Karlsruhe, Germany, 2011.
F. Duhem, F. Muller & P. Lorenzini, “FaRM: Fast
Reconfiguration Manager for reducing reconfiguration time overhead on
FPGA”, ARC symposium, Belfast, UK, 2011.
B.
Ouni, I.
Belaid, F. Muller & M. Benjemaa, “Placement of hardware
tasks on FPGA using the bees algorithm”,
PECCS, Vilamoura, Portugal, 2011.
I.
Belaid, F. Muller & M. Benjemaa, “Optimal
static scheduling of real-time of
dependent tasks on
reconfigurable devices”,
CCCA, Hammamet, Tunisia, 2011.
F. Duhem, F. Muller &
P. Lorenzini, “Transaction-level modeling of dynamically reconfigurable
systems using SystemC”, SAME, Sophia Antipolis, France, 2011.
C. Foucher, F. Muller & A.
Giulieri, “Exploring FPGAs capability to host a HPC design”, IEEE CAS Norchip, Tampere,
Finland, 2010.
I.
Belaid, F. Muller & M. Benjemaa, “New
Three-level resource management for off-line placement of hardware
tasks on reconfigurable
devices”,
ReCoSoC, Karlsruhe, Germany, 2010.
F.
Muhammad & F. Muller, “An
embedded, generic and multiprocessor hardware operating system”,
DASIP, Sophia
Antipolis, France, 2009.
I.
Belaid, F. Muller & M. Benjemaa, “Off-line
placement of reconfigurable
zones and off-line mapping of hardware
tasks on FPGA”,
DASIP, Sophia Antipolis, France,
2009.
I.
Belaid, F. Muller & M. Benjemaa, “Off-line
placement of hardware
tasks on FPGA”,
FPL, Prague, Czech Republic,
2009.
F.
Muller & F.
Muhammad,
“Virtual platform for hw rtos-multiprocessor
hardware rtos”,
DATE, University Booth,
Nice, France, 2009.
Revues
nationales :
P.
Masson, F. Ferrero, F. Muller & G. Jacquemod, “Electronique
analogique et mixte en PeiP dans le réseau Polytech”, J3eA, Hors-série 1 (2017),
vol. 16, 1017, 9 pages, Janvier 2018.
C. Foucher, F. Muller & A.
Giulieri, “Méthodologie dédiée aux applications
parallèles sur
plateforme reconfigurable dynamiquement”,
Technique
et Science Informatiques, Vol. 32, n°
2, pp. 253-280,
2012.
Conférences nationales :
P.
Masson, F. Ferrero, F. Muller & G. Jacquemod, “Electronique analogique
en PEIP2 dans le réseau Polytech”,
Journées
pédagogiques du CNFM, Montepllier, France, 2016.
J.
Rey, T. Degruel, Y. Del Gallo & F. Muller, “Architecture
générique sur FPGA pour une utilisation flexible des IPs
haut niveau de traitement du signal”,
ComPAS,
Neuchatel, Switzerland, 2014.
F. Duhem, F. Muller &
P. Lorenzini, “Dynamic and partial reconfiguration transaction-level
modeling in SystemC”, GdR SoC/SiP, Lyon, France, 2011.
C. Foucher, F. Muller & A.
Giulieri, “Flot de conception d'applications
parallèles sur
plateforme reconfigurable”,
Sympa, Saint-Malo, France, 2011.
I.
Belaid, F. Muller & M. Benjemaa, “Off-line
placement/scheduling of hardware
tasks on reconfigurable
devices”,
GdR SoC/SiP, Cergy-Pontoise, France, 2010.
F. Duhem, F. Muller &
P. Lorenzini, “Services pour des systèmes reconfigurables
dynamiquement”, GdR SoC/SiP,
Cergy-Pontoise, France, 2010.
I.
Belaid, F. Muller, M. Benjemaa & A. Giulieri, “Off-line
placement of hardware
tasks on FPGA”,
GdR SoC/SiP, Paris-Orsa, France, 2019.
C. Foucher, F. Muller & A.
Giulieri, “Implémentation d'un système d'exploitationn
matériel compatible rtems”,
GdR SoC/SiP, Paris-Orsa, France, 2019.
B.
Ouni, F. Muller & M. Benjemaa, “Placement
et ordonnancement des tâches matérielles sur des zones
reconfigurables en utilisant le bees algorithme”,
GdR SoC/SiP, Paris-Orsa, France, 2019.
Brevets et logiciels :
F.
Muller & F. Duhem, “FoRTReSS
version 1.0”,
03.12.2012,
IDDN.FR.0001.420002.00.SP.2014.00.31235, 2012.
F. Muhammad, M. Auguin
& F. Muller, “Procédé
de gestion des préemptions dans un système d'exploitation
temps-rée”,
n° d'application wo/2009/087317, international application n° :
Pct/fr2008/001481, european patent office n° 088699004-2211,
22/10/2008
