---

Résumé :

Pascal Masson est diplomé de l'ENSERG et a obtenu son doctorat à l'INSA de Lyon en 1999. Il est actuellement professeur à l'Université Nice Sophia Antipolis et travaille sur la modélisation et la caractérisation de transistors MOS, ainsi que sur les mémoires.

Pascal Masson (1969) received the M.Sc.E.E. degree from ENSERG and the Ph.D. degree from INSA of Lyon in 1999. He is Professor at the University of Nice and he is working on modeling and characterization of MOS transistors and memories.

---

Domaine d'activité :

Physique des semiconducteurs, mémoires non-volatiles, modélisation compacte

---

Publications :

Chapitres de livre :
 

E. Gerritsen, P. Masson & P. Mazoyer, “Papers selected from the 1th International Conference on Memory Technology and Design”, Solid-State Electronics, vol. 49, n°11, pp. 1713-1874, 2005.

B. De Salvo & P. Masson, “From floating-gate non-volatile memories to silicon nano-crystal memories”, Recent research developments in non-crystalline-solids, Edited by S.G. Pandalie, Transworld Research Network, Vol. 2, 2002.

 

Brevets :

 

R. Bouchakour, V. Bidal, P. Candelier, R. Fournel, P. Gendrier, R. Laffont, P. Masson, J-M. Mirabel & A. Regnier “Non-volatile reprogrammable memory”, Brevet STMicroelectronics, Université de Provence, n° d'application 11/525529, US 7,675,106, 9 Mars 2010.

J.M. Mirabel, A. Régnier, R. Bouchakour, R. Laffont & P. Masson “Floating gate MOS Transistor with double control gate”, Brevet STMicroelectronics, Université de Provence, n° d'application 11/155306, US 7242621, date publication 10 Juillet 2007.

 

Revues internationales :
 

P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Regnier & S. Niel, “Hot-carrier reliability and performance study of a variable gate-to-drain/source overlap transistor”, Microelectronic Reliability, vol. 139, 6 p., 2022.

Q. Hubert, M. Carmona, B. Rebuffat, J. Innocenti, P. Masson, L. Masoero, F. Julien, L. Lopez, P. Chiquet, “All regimes mobility extraction using split C–V technique enhanced with charge-sheet model”, Solid-State Electronics, Vol. 111, p. 52–57, 2015.

Y. Joly, L. Lopez, L. Truphemus, JM. Portal, H. Aziza, F. Julien, P. Fornara, P. Masson, JL. Ogier & Y. Bert, “Gate Voltage Matching Investigation for Low Power Analog Applications”, IEEE Transactions on Electron Devices, 2013.

G. Just, V. Della Marca, A. Régnier, J-L. Ogier, J. Postel-Pellerin, F. Lalande, J-M Portal & P. Masson, “Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability, Journal of Low Power Electronics, vol. 8, pp. 717-724, 2012.

Y. Joly, L. Lopez, J.-M. Portal, H. Aziza, P. Masson,J.-L. Ogier, Y. Bert, F. Julien & P. Fornara, “Threshold voltage asymmetric degradationon octagonal MOSFET during HCI stress”, IEE Electronics Letters, vol. 48, n°14, pp. 879-881-6232, 2012.

P. Chiquet, P. Masson, R. Laffont, G. Micolau, J. Postel-Pellerin, F. Lalande, B. Bouteille & J-L. Ogier, “Investigation of the effects of constant voltage stress on thin SiO2 layers using dynamic measurement protocols”, Microelectonics Reliability, vol. 52, pp. 18195-1900, 2012.

R. Llido, P. Masson, A. Regnier, V. Goubier, G. Haller, V. Pouget & D. Lewis, “Effects of 1064 nm laser on MOS capacitor”, Microelectonics Reliability, vol. 52, pp. 1816-1821, 2012.

P. Mazoyer, S. Puget, G. Bossu, P. Masson, P. Lorenzini & J.M. Portal, “Thin film embedded memory solutions”, Current Applied Physics, vol. 10, n°1, pp. e9-e12, 2010.

S. Puget, G. Bossu, P. Masson, P. Mazoyer, R. Ranica, A. Villaret, P. Lorenzini, J.M. Portal, D. Rideau, G. Ghibaudo, R. Bouchakour, G. Jacquemod & T. Skotnicki, “Modelling the Independent Double Gate Transistor in Accumulation Regime for 1T DRAM Application”, IEEE Transaction On Electron Devices, vol. 57, n°4, pp. 855-864, 2010.

R. Ranica, A. Villaret, P. Malinge, P. Candelier, P. Masson, R. Bouchakour, P. Mazoyer & T. Skotnicki, “Modelling of the 1T-bulk capacitor-less DRAM cell with improved performances : the way to scaling”, Solid-State Electronics, vol. 49, n°11, pp. 1759-1766, 2005.

F. Gilibert, D. Rideau, A. Dray, F. Agut, M. Minondo, A. Juge, P. Masson & R. Bouchakour, “Characterization and modeling of gate-induced-drain-leakage”, IEICE Transactions on Electronics, pp. 829-837, 2005.

L. Perniola, S. Bernardini, G. Iannaccone, P. Masson, B. DeSalvo, G. Ghibaudo & C. Gerardi, “Analytical Model of the Effects of a Nonuniform Distribution of Stored Charge on the Electrical Characteristics of Discrete-Trap Nonvolatile Memories”, IEEE Transactions on Nanotechnology, vol. 4, n°3, pp. 360-368, May 2005.

R. Ranica, A. Villaret , P. Mazoyer, S. Monfray, D.Chanemougame, P. Masson, C. Dray, P. Waltz, R. Bez, R. Bouchakour & T. Skotnicki, “A new 40nm SONos structure based on backside trapping for nanoscale memories”, IEEE Transactions on Nanotechnology, vol. 4, n°5, pp. 581-587, 2005.

A. Villaret, R. Ranica, P. Malinge, P. Masson, P. Mazoyer, P. Candelier & T. Skotnicki, “Further Insight on the Modelling and Characterization of Triple-Well Capacitorless DRAMs”, IEEE Transactions on Electron Devices, vol. 52, n°11, pp. 2447-2454, 2005.

S. Bernardini, P. Masson, M. Houssa & F. Lalande, “Origin and repartition of the oxide fixed charges generated by electrical stress in memory tunnel oxide”, Applied Physic Letters, vol. 84, n°21, pp. 4251-4253, 2004.

A. Villaret, R. Ranica, P. Masson, P. Malinge, P. Mazoyer, P. Candelier, F. Jacquet, S. Cristoloveanu & T. Skotnicki, “Mechanisms of charge modulation in floating body of triple-well N-MOSFET capacitor-less DRAMs”, Microelectronic Engineering, vol. 72, pp. 434-439, 2004.

L. Lopez, P. Masson, D. Née & R. Bouchakour, “Temperature and drain voltage dependence of Gate Induce Drain Leakage”, Microelectronic Engineering, vol. 72, pp. 101-105, 2004.

S. Bernardini, P. Masson & M. Houssa, “Effect of fixed dielectric charges on tunneling transparency in MIM and MIS structures”, Microelectronic Engineering, vol. 72, pp. 90-95, 2004.

R. Laffont, P. Masson, S. Bernardini, R. Bouchakour & J.M. Mirabel, “A new floating compact model applied to Flash memory cell”, Journal of Non-Crystalline Solids, vol. 322, n°1-3, pp. 250-255, 2003.

P. Masson, J.L. Autran, M. Houssa, X. Garros & C. Leroux, “Frequency characterization and modeling of interface traps in metal-oxide-semiconductor structures with HfO2 gate dielectrics from a capacitance point-of-view”, Applied Physic Letters, vol. 81, n°18, pp. 3392-3394, 2002.

L. Militaru, P. Masson & G. Geguan, “Three level charge pumping on a single interface trap”, Applied Physic Letters, vol. 23, n°2, pp. 94-96, 2002.

P. Masson, J.L. Autran & D. Munteanu, “DYNAMOS : a numerical MOSFET model including quantum-mechanical and near-interface trap transient effects”, Solid-State Electronics, vol. 46, pp. 1051-1059, 2002.

C.E. Weintraub, E. Vogel, J.R. Hauser, N. Yang, V. Misra, J.J. Wortman, J. Ganem & P. Masson, “Study of low-frequency charge pumping on thin stacked dielectrics”, IEEE Transactions on Electron Devices, vol. 48, n°12, pp. 2754-5762, 2001.

B. De Salvo, G. Ghibaudo, G. Pananakakis, P. Masson, T. Baron, N. Buffet, A. Fernandes & B. Guillaumot, “Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices”, IEEE Transactions on Electron Devices, vol. 48, n°8, pp. 1789-1799, 2001.

P. Masson, J.L. Autran & G. Ghibaudo, “An improved time domain analysis of the charge pumping current”, Journal of Non-Crystalline Solids, vol. 280, n°1-3, pp. 255-260, 2001.

J.L. Autran, P. Masson, N. Freud, C. Raynaud & C. Riekel, “Micro-Irradiation experiments in MOS transistors using synchrotron radiation”, IEEE Transactions on Nuclear Science, vol. 47, n°3, pp. 574-579, 2000.

P. Masson, P. Morfouli, J.L. Autran & J.J. Wortman, “Electrical characterization of n-channel MOSFET's with oxynitride gate dielectric formed by Low-Pressure Rapid Thermal Chemical Vapor Deposition”, Microelectronic Engineering, vol. 48, n°1-4, pp. 211-214, 1999.

P. Masson, P. Morfouli, J.L. Autran, J. Brini, B. Balland, E.M. Vogel & J.J. Wortman, “Electrical properties of oxynitride films using noise and charge pumping measurements”, Journal of Non-Crystalline Solids, vol. 245, n°1-3, pp. 54-58, 1999.

P. Masson, J.L. Autran & J. Brini, “On the tunneling component of charge pumping current in Ultra-thin gate oxide MOSFET's”, IEEE Electron Device Letters, vol. 20, n°2, pp. 92-94, 1999.

P. Masson, G. Ghibaudo, J.L. Autran, P. Morfouli & J. Brini, “Influence of the quadratic mobility degradation factor on the low frequency noise in MOS transistors”, IEE Electronics Letters, vol. 34, n°20, pp. 1977-1978, 1998.

P. Masson, J.L. Autran, C. Raynaud, O. Flament & P. Paillet, “Surface potential determination in irradiated MOS transistors combining current-voltage and charge pumping measurements”, IEEE Transactions on Nuclear Science, vol. 45, n°3, pp. 1355-1364, 1998.

Communications invitées :

 

G. Just, V. Della Marca, A. Regnier, J.-L. Ogier, J. Postel-Pellerin, F. Lalande, J.-M Portal & P. Masson, “Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability”, VARI, Sophia Antipolis, France, 2012.

J.L. Autran, P. Masson & G. Ghibaudo, “Challenges in interface trap characterization of deep sub-micron MOS devices using charge pumping techniques ”, MRS, Boston, MA, pp. 275-288, 1999.

 

Conférences internationales :

 

P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Regnier & S. Niel, “Schmitt trigger to benchmark the performance of a new zero-cost transistor”, ICECS, Glasgow, UK, 2022.

P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Regnier & S. Niel, “Hot-carrier reliability and performance study of a variable gate-to-drain/source overlap transistor”, ESREF, Berlin, Germany, 2022.

P. Devoge, H. Aziza, P. Lorenzini, A. Malherbe, F. Julien, A. Marzaki, A. Regnier & S. Niel, “Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor”, ISCAS, Austin, USA, 2022.

P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau,  T. Cabout, A. Regnier & S. Niel, “Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation”, IEEE IIRW, Fallen Leaf Lake, USA, 2022.

D. Morillon, P. Masson, F. Julien, P. Lorenzini, J. Goy, C. Pribat, O. Gourhant, T. Kempf, J.-L. Ogier, A. Villaret, G. Ghezzi, N. Cherault & S. Niel, “Gate Oxide Degradation Assessment by Electrical Stress and Capacitance Measurements,” International Integrated Reliability Workshop, Fallen Leaf Lake, CA, USA, 2018.

T. Kempf, V. Della Marca, L. Baron, F. Maugain, F. La Rosa, S. Niel, A. Regnier, J.-M. Portal & P. Masson  “Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip”, International Reliability Physics Symposium, Burlingame, USA, 2018.

T. Kempf, V. Della Marca, P. Canet, A. Regnier, P. Masson & J.-M. Portal, “A new method for chip test and single 40nm NOR Flash cell electrical parameters correlation using a cast structure”, International Symposium on VLSI Technology, Systems and Application, Hsinchu, Taiwan, 2018.

T. Kempf, M. Mantelli, F. Maugain, A. Regnier, J.-M. Portal, P. Masson, J.-M. Moragues, M. Hesse, V. Della Marca, F. Julien & S. Niel, “Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array”, International Integrated Reliability Workshop, Fallen Leaf Lake, USA, 2017.

D. Morillon, C. Pribat, F. Julien, N. Cherault, J. Goy, O. Gourhant, J.-L. Ogier, P. Masson, G. Ghezzi, T. Kempf, J. Delalleau, A. Villaret, J.-C. Grenier & S. Niel, “Study of HTO-based alternative gate oxides for high voltage transistors on advanced eNVM technology”, International Integrated Reliability Workshop, Fallen Leaf Lake, USA, 2017.

D. Morillon, F. Julien, J. Coignus, A. Toffoli, L. Welter, C. Jahan, J.-P. Reynard, E. Richard & P. Masson, “High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process”, IEEE ICMTS, Grenoble, France, 2017.

P. Chiquet, J. Postel-Pellerin, C. Tuninetti, S. Souiki-Figuigui & P. Masson, “Effect of short pulsed Program/Erase cycling on Flash memory device”, IMEKO, Milan, Italy, 2016.

J. Innocenti, L. Welter, N. Borrel, F. Julien, J.M. Portal, J. Sonzogni, L. Lopez, P. Masson, S. Niel, P. Dreux & J. Castellan, “Dynamic current reduction of CMOS digital circuits through design and process optimization”, VARI/PATMOS, Salvador Bahia, Brazil, 2015.

J. Innocenti, F. Julien, J. M. Portal, L. Lopez, Q. Hubert, P. Masson, J. Sonzogni, S. Niel & A. Regnier, “Layout Optimizations to Decrease Internal Power and Area in Digital CMOS Standard Cells”, Inf. Commun. Technol. Electron. Microelectron., Opatija, Croatia, 2015.

J. Innocenti, C. Rivero, F. Julien, J. M. Portal, Q. Hubert, G. Bouton, P. Fornara, L. Lopez & P. Masson, “NMOS Drive Current Enhancement by Reducing Mechanical Stress Induced by Shallow Trench Isolation,” IEEE EDSSC, Singapore, Singapore, pp. 395–398, 2015.

J. Innocenti, F. Julien, J. M. Portal, L. Lopez, Q. Hubert, P. Masson, J. Sonzogni, S. Niel & A. Regnier, “Layout Optimizations to Decrease Internal Power and Area in Digital CMOS Standard Cells”, Inf. Commun. Technol. Electron. Microelectron., Opatija, Croatia, 2015.

B. Rebuffat, P. Masson, J-L. Ogier  M. Mantelli & R. Laffont, “Effect of AC Stress on Oxide TDDB and Trapped Charge in Interface States”, ISIC, Singapore, Singapore, 2014.

R. Rebuffat, V. Della Marca, J-L. Ogier, & P. Masson, “Effect of Ions Presence in the SiOCH Inter Metal Dielectric Structure”, ESSDERC, 2013.

P. Chiquet, P. Masson, G. Micolau, R. Laffont, F. Lalande, J. Postel-Pellerin & A. Regnier, “Determination of physical properties of semiconductor-oxide-semiconductor structures using a new fast gate current measurement protocol”, IEEE ICSD, Bologna, Italy, 2013.

G. Just, J.-L. Ogier, A. Regnier, J. Postel-Pellerin, F. Lalande & P.Masson, “Impact of Poly-Reoxidation Process Step on Tunnel Oxide Reliability: Charge Trapping and Data Retention”, Symposium “SiO2, Advanced Dielectrics and Related Devices, June 2012.

P. Chiquet, P. Masson, G. Micolau, R. Laffont, J. Postel-Pellerin, F. Lalande, B. Bouteille & A. Regnier, “A new fast gate current measurement protocol for the study of transient regimes in metal-oxide-semiconductor structures”, Symposium “SiO2, Advanced Dielectrics and Related Devices, June 2012.

P. Chiquet, P. Masson, R. Laffont, G. Micolau, J. Postel-Pellerin, F. Lalande, B. Bouteille & J-L. Ogier, “Investigation of the effects of constant voltage stress on thin SiO2 layers using dynamic measurement protocols”, ESREF, October 2012.

R. Llido, P. Masson, A. Regnier, V. Goubier, G. Haller, V. Pouget & D. Lewis, “Effects of 1064 nm laser on MOS capacitor”, ESREF, October 2012.

Y. Joly, L. Lopez, J.-M. Portal, H. Aziza, P. Masson, J.-L. Ogier, Y. Bert, F. Julien & P. Fornara, “Octagonal MOSFET: Reliable Device for Low Power Analog Applications”, ESSDERC, Spetember 2013.

S. Puget, G. Bossu, P. Masson, P. Mazoyer, J-M. Portal, P. Lorenzini, D. Rideau, R. Bouchakour & T. Skotnicki, “Quantum Effect Modeling in Thin Film Independent Double Gate Capacitorless eDRAM”, ESSDERC, Athens, Greece, September 2009.

S. Puget, J-M. Portal, P. Masson, P. Mazoyer, G. Bossu, P. Lorenzini, R. Bouchakour & T. Skotnicki, “Optimization of Independent Double Gate Floating Body Cell DRAM Performance by Technology Screening”, Silicon Nano-Workshop, Kyoto, Japan, June 2009.

S. Puget, G. Bossu, C. Fenouillet-Beranger, P. Perreau, P. Masson, P. Lorenzini, P. Mazoyer, J-M. Portal, R. Bouchakour & T. Skotnicki, “DFDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications”, International Memory Workshop, Montery, CA, May 2009.

G. Bossu, S. Puget, P. Masson, J-M. Portal, R. Bouchakour, P. Mazoyer & T. Skotnicki, “Independent Double Gate - Potential for Non-Volatile Memories”, IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 2008.

S. Puget, G. Bossu, P. Mazoyer, J.M. Portal, P. Masson, R. Bouchakour & T. Skotnicki, “On the Potentiality of Planar Independent Double Gate for Capacitorless eDRAM”, IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 2008.

S. Puget, G. Bossu, F. Berthollet, P. Mazoyer, J.M. Portal, P. Masson, R. Bouchakour & T. Skotnicki, “1TBulk eDRAM Using Gate-Induced Drain-Leakage (GIDL) Current for High Speed and Low Power applications”, International conference on Solid State Devices and Materials, Ibaraki, Japan, September 2008.

G. Bossu, A. Demolliens, S. Puget, P. Masson, J.M. Portal, R. Bouchakour, P. Mazoyer & T. Skotnicki, “A new embedded NVM thin film cell for low voltage applications”, International conference on Solid State Devices and Materials, Ibaraki, Japan, September 2008.

S. Puget, G. Bossu, C. Guerin, R. Ranica, A.Villaret, P. Masson, J-M. Portal, R. Bouchakour, P. Mazoyer, V. Huard & T. Skotnicki, “1TBulk eDRAM a reliable concept for nanometre scale high density and low power applications”, 2nd International Conference on Memory Technology and Design, Giens, France, May 2007.

R. Wacquez, R. Cerutti, P. Coronel, A. Cros, D. Fleury, A. Pouydebasque, J. Bustos, S. Harrison, N. Loubet, S. Borel, D. Lenoble, D. Delille, F. Leverd, F. Judong, M.P. Samson, N. Vuillet, B. Guillaumot, T. Ernst, P. Masson & T. Skotnicki, “A Novel Self Aligned Design Adapted Gate All Around (SADAGAA) MOSFET including two stacked Channels: A High Co-Integration Potential”, SSDM, 2006.

A. Regnier, J.M. Portal, H. Aziza, P. Masson, R. Bouchakour, C. Relliaud, D. Née & J.M. Mirabel, “EEPROM Compact Model with SILC Simulation Capability”, IEEE Non Volatile Memory Technology Symposium, San Mateo, CA, pp. 26-30, 2006.

A. Régnier, B. Saillet, J.M. Portal, B. Delsuc, R. Laffont, P. Masson & R. Bouchakour, “MM11 Based Flash Memory Cell Model Including Characterization Procedure”, IEEE International Symposium on Circuits and Systems, Kos, Greece, pp. 3518-3521, 2006.

S. Puget, G. Bossu, A. Regnier, R. Ranica, A. Villaret, P. Masson, G. Ghibaudo, P. Mazoyer & T. Skotnicki, “Quantum effects influence on thin silicon film capacitor-less DRAM performance”, International SOI conference, New York, NY, pp. 157-158, 2006.

G. Bossu, C. Charbuillet, R. Ranica, A. Villaret, D. Chanemougame, S. Monfray, S. Borel, F. Leverd, P. Masson & P. Mazoyer, “ eRAM: A quasi non volatile low power memory cell”, VLSI Silicon Nanoworkshop, 2006.

R. Ranica, A. Villaret, P. Malinge, P. Candelier, P. Masson, R. Bouchakour, P. Mazoyer & T. Skotnicki, “1T-Bulk DRAM cell with improved performances: the way to scaling”, ICMTD, pp. 59-52, 2005.

K.Castellani-Coulié, D. Munteanu, J.L. Autran, V. Ferlet-Cavrois, P. Paillet & P. Masson, “Device simulation study of SEU in SRAMs based on double-gate MOSFETs”, ICMTD, Giens, France, pp. 93-96, 2005.

L. Lopez, P. Masson, D. Nee & R. Bouchakour, “A model to explain the C-V curves of DRAM capacitors with silicon electrodes and trapping dielectrics”, ICMTD, Giens, France, pp. 85-88, 2005.

R. Ranica, A. Villaret, P. Malinge, G. Gasiot, P. Mazoyer, P. Roche, P. Candelier, F. Jacquet, P. Masson, R. Bouchakour, R. Fournel, J.P. Schoellkopf & T. Skotnicki, “Scaled 1T-Bulk devices built with CMOS 90 nm technology for low-cost eDRAM applications”, VLSI Technology Symposium, Kyoto, Japan, pp. 38-39, 2005.

R. Ranica, A. Villaret, C. Fenouillet-Beranger, P. Malinge, P. Mazoyer, P. Masson, D. Delille, C. Charbuillet, P. Candelier & T. Skotnicki, “A capacitor-less DRAM cell on very thin film and 75nm gate length Fully Depleted device for high density embedded memories”, IEDM, pp. 277-280, 2004.

L. Perniola, S. Bernardini, G. Iannaccone, B. De Salvo, G. Ghibaudo, P. Masson & C. Gerardi, “Channel Hot Electron Impact on Electrical Characteristics of Discrete-Trap Memories”, ESSDERC, Leuven, Belgium, pp. 249-252, 2004.

X. Cuinet, S. Bernardini, P. Masson & L. Raymond, “Simulation of nanometric roughness on a MOS capacitance”, 5nd French-Italian Symposium on SiO2 and advanced dielectrics, 2004.

R. Ranica, A. Villaret, P. Mazoyer, S. Monfray, D.Chanemougame, P. Masson, C. Dray, P. Waltz, R. Bez & T. Skotnicki, “A new SONos structure based on backside trapping for nanoscale memory applications”, VLSI Silicon Nanoworkshop, 2004.

R. Ranica, A. Villaret, P. Malinge, P. Mazoyer, D. Lenoble, P. Candelier, F. Jacquet, P. Masson, R. Bouchakour, R. Fournel, J.P. Schoellkopf & T. Skotnicki, “A One Transistor Cell on Bulk Substrate (1T-Bulk) for Low-Cost and High Density eDRAM”, VLSI Technology Symposium, Hawai, HI, pp. 128-129, 2004.

L. Lopez, D. Née, P. Masson & R. Bouchakour, “A low cost test vehicule for embedded DRAM capacitor investigation and monitoring of the process”, IRPS, pp. 498-501, 2004.

S. Bernardini, J.M. Portal & P. Masson, “A tunneling model for gate oxide failure in deep sub-micron technology”, DATE, pp. 1404-1406, 2004.

S. Bernardini, J.M. Portal, P. Masson, J.M. Gallière & M. Renovell, “Impact of gate reduction failure on analog application : example of the current mirror”, LATW, Cartagena, Colombia, pp. 12-17, 2004.

S. Bernardini, P. Masson, M. Houssa & F. Lalande, “Impact of oxide charge trapping on I-V characteristics of MIM capacitor”, ESSDERC, Estoril, Portugal, pp. 589-592, 2003.

L. Lopez, P. Masson, D. Née & R. Bouchakour, “Temperature and drain voltage dependence of Gate Induce Drain Leakage”, INFOS, Barcelona, Spain, 2003.

S. Bernardini, P. Masson & M. Houssa, “Effect of fixed dielectric charges on tunneling transparency in MIM and MIS structures”, INFOS, Barcelona, Spain, 2003.

S. Bernardini, R. Laffont, P. Masson, G. Ghibaudo, S. Lombardo, B. De Salvo, & C. Gerardi, “A predictive nano-crystal Flash memory simulator”, 4rd European Workshop on Ultimate Integration of Silicon, Udine, Italy, pp. 143-146, June 2003.

B. Guillaumot, X. Garros, F. Lime, K. Oshima, J.A. Chrobovzek, P. Masson, R. Truche, A.M. Papon, F. Martin, J.F Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, T. Skotnicki & S. Deleonibus, “Metal gate high-K integration for advanced CMOS devices”, 8th International Symposium on Plasma and Process Induced Damage, pp. 56-60, April 2003.

R. Laffont, P. Masson, P. Canet, B. Delsuc, R. Bouchakour & J.M. Mirabel, “Fowler Nordheim current determination during EEPROM cell operation”, ESSDERC, Estoril, Portugal, pp. 71-74, 2003.

A. Villaret, R. Ranica, P. Masson, P. Mazoyer, S. Cristoloveanu & T. Skotnicki, “Mechanisms of charge modulation in floating body of triple-well N-MOSFET capacitor-less DRAMs”, INFOS, Barcelona, Spain, 2003.

B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J.A. Chroboczek, P. Masson, R. Truche, A.M. Papon, F. Martin, J.F. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J.L. Autran, T. Skotnicki & S. Deleonibus, “75 nm damascene metal gate and high-k integration for advanced CMOS devices”, IEDM, San Francisco, CA, December 2002.

B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J.A. Chroboczek, P. Masson, R. Truche, A.M. Papon, F. Martin, J.F. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J.L. Autran, T. Skotnicki & S. Deleonibus, “75 nm damascene metal gate and high-k integration for advanced CMOS devices”, IEDM, San Francisco, CA, December 2002.

R. Laffont, P. Masson, R. Bouchakour, S. Bernardini & J.M. Mirabel, “A new Flash physical model based on Pao and Sah approach”, 4nd French-Italian Symposium on SiO2 and advanced dielectrics, Florence, Italy, September 2002.

P. Masson, L. Militaru, B. DeSalvo, G. Ghibaudo, V. Celibert & T. Baron, “Nano-crystal memory devices characterization using the charge pumping technique”, ESSDERC, Florence, Italy, pp. 235-238, 2002.

P. Masson, J.L. Autran, X. Garros & C. Leroux, “Frequency characterization and modeling of interface traps in metal-oxide-semiconductor capacitors with polysilicon gate and HfO2 high-K dielectrics”, 3rd European Workshop on Ultimate Integration of Silicon, Munich, Germany, June 2002.

A. Fernandez, B. DeSalvo, T. Baron, J.F. Damlencourt, A.M. Papon, D. Lafond, D. Mariolle, B. Guillaumot, P. Besson, P. Masson, G. Ghibaudo, G. Pananakakis, F. Martin & S. Haukka, “Memory characteristics of Si quantum dot devices with SiO2/Al2O3 tunneling dielectrics”, IEDM, Washington, MA, December 2001.

A. Fernandez, B. DeSalvo, P. Masson, G. Pananakakis, G. Ghibaudo, T. Baron, N. Buffet, D Mariolle & G. Ghibaudo, “Electrical characterization of memory-cell structure employing ultra-thin Al2O3 film as storage node”, ESSDERC, Nuremberg, Germany, September 2001.

L. Militaru, P. Masson, V. Celibert & C Leroux, “Single Trap Characterization in 50nm MOS Transistors by Charge Pumping Measurements”, ESSDERC, Nuremberg, Germany, September 2001.

B. De Salvo, G. Ghibaudo, G. Pananakakis, P. Masson, A. Fernandes, T. Baron, N. Buffet, D. Mariolle & B. Guillaumot, “Electrical characterisation and modeling of memory-cell structures employing discrete-trap type storage nodes”, Silicon Nanoelectronics Workshop, Kyoto, Japan, June 2001.

P. Masson, J.L. Autran & D. Munteanu, “DYNAMOS : a numerical MOSFET model including quantum-mechanical and near-interface trap transient effects”, 2nd European Workshop on Ultimate Integration of Silicon, Grenoble, France, February 2001.

J.L. Autran, M. Bidaud, N. Emonet, P. Masson & A. Poncet, “Quantum mechanical modeling of gate tunneling currents in metal-oxide-semiconductor devices”, 3nd French-Italian Symposium on SiO2 and advanced dielectrics, Fuveau, France, June 2000.

P. Masson, J.L. Autran & G. Ghibaudo, “An improved time domain analysis of the charge pumping current”, 3nd French-Italian Symposium on SiO2 and advanced dielectrics, Fuveau, France, June 2000.

C. Raynaud, J.L. Autran, P. Masson, M. Bidaud & A. Poncet, “Analysis of MOS device capacitance-voltage characteristics based on the self-consistent solution of the schrödinger and Poisson equations”, MRS, Boston, MA, pp. 159-164, 1999.

B. De Salvo, R. Clerc, P. Masson, Y.A. Ahouassa & G. Ghibaudo, “Electrical characterization and modelling of ultra-thin (1.8-3.4 nm) gate oxides”, ESSDERC, Leuven, Belgium, pp. 168-171, 1999.

J.L. Autran, P. Masson, N. Freud, C. Raynaud & C. Riekel, “Micro-Irradiation experiments in MOS transistors using synchrotron radiation”, 5th IEEE European Conference on radiation and its Effects on Components and Systems, Fontevraud, France, pp. 256-261, 1999.

P. Masson, P. Morfouli, J.L. Autran & J.J. Wortman, “Electrical characterization of n-channel MOSFET's with oxynitride gate dielectric formed by Low-Pressure Rapid Thermal Chemical Vapor Deposition”, INFOS, Erlangen, Germany, June 1999.

P. Masson, P. Morfouli, J.L. Autran, J. Brini, B. Balland, E.M. Vogel & J.J. Wortman, “Electrical characterization of thin RTO and RTCVD silicon oxynitride films using noise and charge pumping measurements”, 2nd French-Italian Symposium on SiO2 and advanced dielectrics, L'Aquila, Italy, June 1998.

P. Masson, J.L. Autran, C. Raynaud, O. Flament & P. Paillet, “Surface potential determination in irradiated MOS transistors combining current-voltage and charge pumping measurements”, 4th IEEE European Conference on radiation and its Effects on Components and Systems, Cannes, France, pp. 26-35, 1997.

 

Revues nationales :

 

P. Masson, F. Ferrero, F. Muller & G. Jacquemod, “Electronique analogique et mixte en PeiP dans le réseau Polytech”, J3EA, Hors-série 1 (2017), Vol. 16, 1017, Janvier 2018.

M. Hesse, A. Regnier & P. Masson, “Développement de mémoires non-volatiles embarquées pour les plateformes technologiques avancées 40nm et 28nm”, J3EA, Vol. 16, 1003, 2017.

 

Conférences nationales :

 

D. Morillon, F. Julien & P. Masson, “High and medium voltage transistors for embedded non-volatile memories on 28nm FDSOI technology”, JNRDM, Strasbourg, 2017.

D. Morillon, F. Julien & P. Masson, “Etude et développement de transistors haute tension et de cellules mémoires non volatiles en 28nm FDSOI”, JNRDM, Toulouse, France, 2016.

M. Hesse, A. Regnier & P. Masson, “Développement de mémoires non-volatiles embarquées pour des plateformes technologiques avancées 40nm et 28nm”, JNRDM, Toulouse, France, 2016, Prix CNFM du meilleur Poster.