Résumé
:
Yves Leduc obtained respectively his
Master and Ph.D. in Electric engineering in 1975 and 1979 from the
Catholic University of Louvain in Belgium. He joined Texas Instruments
France in 1980 as an IC design endineer in the Telecom design group. In
1990, and 1991, he worked in the Central R&D Labs of TI Dallas to
establish the foundations of the design modeling and gigh level
simulation of Sigma-Delta converters. Back to France, he created the
Mixed Signal Design team of TI France in 1995, working on the first ICs
of the GSM platforms of TI. He was elected TI Fellow in 1998 and
managed the Advanced System Technology team in 2000. In 2010, he moved
to Polytech Nice-Sophiaat the University of Nice Sophia Antipolis,
where he holding the Texas Instruments Chair.
Domaine d'activité :
Conception de circuits
et systèmes, électronique analogique et mixte, PLL,
Capacités commutées, NAPA : modélisation
système
Publications
:
Brevets
:
P. Audebert, E. de
Foucauld, Y. Leduc, G. Jacquemod, Z. Wei & P. Lorenzini, “Circuit
électronique élémentaire pour étage
amplificateur ou de recopie de signaux analogiques”, Brevet
Français CEA-LETI et UNS, 6 avril 2017, WO2017055709 A1,
PCT/FR2016/052394, étendu Europe 2016784226, extension USA, 6
mars 2018, US 15757972.
G. Jacquemod, E. de
Foucauld, Y. Leduc, A. Fonseca & P. Lorenzini,
“Procédé et dispositif d'auto-calibration de circuits
multigrilles”, Brevet
Français CEA-LETI et UNS, 10 avril 2015, FRA 1553096,
étendu Europe, 8 avril
2016, 16164459.6-1810, extension USA, 13 octobre 2016, US20160301365.
Y. Leduc,
N. Messina, K.J. Taylor, L.N. Hutter, J.O. Smith, B.L.
Williams, A.R. Singh, S.R. Summerflet & D.L. Callahan, “Circuit
logic
embedded within IC protective layer”, Brevet TI, United States Patent
Application 20090020313, 22 January 2009.
Y. Leduc,
N. Messina, C. Duvvury & K.P. Wachtler, “In package esd
protections of IC using a thin film polymer”, Brevet TI, United States
Patent
Application 20080278873, 17 Mars 2008.
Revues
internationales
:
M. Moign,
G. Jacquemod, J.-P. Leca & Y. Leduc, “Analysis,
modeling and reduction of the SSN effects on an integrated circuit”, IEEE Electromagetic Compatibility
Magazine, vol. 11, Issue 4, pp. 67-77, 2022.
Z.
Wei, G. Jacquemod, Y. Leduc, E. de Foucauld, J. Prouvee & B.
Blampey, “Reducing the short
channel effect of transistors and reduing the size of analog circuits”,
Active and Passive Electronic Components,
Vol. 2019,
Article ID 4578501, 9 pages, 2019.
Z. Wei, G. Jacquemod,
P. Lorenzini, F. Hameau, E. de Foucauld & Y. Leduc, “Study
and reduction of vairability in 28nm Fully
Depleted Silicon
On Insulatot technology”, Journal of Low Power
Electronics, vol. 12, n° 1,
p. 64-73, 2016.
G. Jacquemod, A.
Fonseca, E. de Foucauld, Y. Leduc & P. Lorenzini, “2.45 GHz 0.8
mW voltage-controlled
ring oscillator (VCRO) in 28 nm Fully Depleted Silicon On Insulator
(FDSOI)
Technology”, Frontiers of Materials Science, vol. 9, Issue 2,
p.
156-162, 2015.
A. Fonseca, E. de
Foucauld, P. Lorenzini & G. Jacquemod, “Low power 28nm FDSOI
2.45 GHz PLL”, Journal of Low
Power Electronics, vol. 10, n° 1, p. 149-162,
2014.
Y. Vaiarello, W.
Tatinian, Y. Leduc, N. Veau & G. Jacquemod, “Ultra-Low-Power
Audio Communication System for Cochlear Implant Application”, Journal
of Low
Power Electronics, vol. 8, n°5, pp. 706-716, 2012.
Y. Vaiarello, W.
Tatinian, Y. Leduc, N. Veau & G. Jacquemod,
“Ultra low power radio microphone for cochlear implant application”, IEEE
Journal of Emerging and Selected Topics in Circuits And Systems,
vol. 1,
n°4, pp. 622-630, 2011.
Communications
invitées :
Y.
Leduc, “An
efficient solution to simulate mixed-signal circuits in C”, NewCAS, Tutorial,
Munich, Germany, 2019.
G.
Jacquemod, Z. Wei, Y.
Leduc, E. de Foucauld & J. Prouvee,
“Reducing small channel effect of UTBB-FDSOI transitor for current
mirror application”, ICSS, Honolulu, USA, 2019.
Y.
Leduc, “Deep learning: our
digital assistants cannot withstand any further to be idiot savants”, NewCAS, Keynote,
Montreal,
Canada, 2018.
Panel
“Challenges
in the Internet of Things”, Moderator : M. Bayoumi, Panelists : N.
Basile, L.
Jure, Y. Leduc, F. Rivet & F. Theoleyre, NewCAS,
Strasbourg, France,
2017.
G.
Jacquemod, Y. Leduc & C. Luxey, “Microphone sans fil
pour implant cochléaire”, FETCH,
Mont Tremblant, Canada, 2017.
G.
Jacquemod & Y. Leduc, “FDSOI
technology and new design”, SETIT, Tutorial, Hammamet, Tunisia,
2016.
Y.
Leduc, G. Jacquemod, Z. Wei, J. Modad, P. Lorenzini, & E. de
Foucauld, “La
logique complémentaire, une
opportunité offerte par le FDSOI pour l'intégration de
circuits mixtes dans les
technologies les plus avancées”, FETCH, Villard-de-Lans,
France, 2016.
G.
Jacquemod, E. de Foucauld, Y. Leduc, F. Hameau, Z. Wei, J. Modad &
P.
Lorenzini, “VCRO
design in 28 nm FDSOI technology using fully complementary inverters”, ICSS,
Phuket, Thailland, pp. 63-64, 2015.
Y.
Leduc, Z.
Wei, J. Modad, M.A. Garcia-Perez,
E. de Foucauld, P. Lorenzini & G. Jacquemod, “Digital
complementary logic in 28
nm FDSOI
technology
to address
the next nanoelectronic challenges”, BIT'S 5th Annual World
Congress of Nano
Science & Technology, Xi'an, China, pp. 172, 2015.
G.
Jacquemod, Y. Leduc, P.
Lorenzini,
E. de Foucauld & A. Fonseca, “Self-calibration
of analog and mixed cells using back-gate auto-biasing transistor
in 28
nm FDSOI technology and beyond”, Nanotechnology
and
Materials Science, Dubai, UAE, pp. 97, 2015.
G.
Jacquemod, A. Fonseca, E. de Foucauld, Y. Leduc & P. Lorenzini, “2.45 GHz 0.8 mW VCRO in FDSOI 28
nm technology”, ICSS,
Hong Kong,
China, pp. 74-75, 2014.
A.
Fonseca, G. Jacquemod, Y. Leduc, E. de Foucauld & P. Lorenzini, “VCO Design in SOI technologies”, NEWCAS,
Special Session «Frequency synthesis – New designs, new
technologies»,
Trois Rivières, Canada, 2014.
G.
Jacquemod, A. Fonseca, Y. Leduc, E. de Foucauld & P. Lorenzini, “Analog Design in FDSOI 28
nm technology and
beyond”, CISIS,
3rd Annual World Congress of Emerging InfoTech, Dalian, China, 2014.
Y. Leduc & G.
Jacquemod, “NAPA, un compilateur construit pour la simulation rapide de
systèmes hétérogènes présents ou
futurs", FETCH, Ottawa, Canada, P.
15, 2014.
A. Fonseca, E. de
Foucauld, P. Lorenzini & G. Jacquemod, “CMOS technology beyond 22
nm”, ICSS, Las Vegas, USA, pp. 152-153, 2013.
G. Jacquemod, Y.
Vaiarello, Y. Leduc & C. Luxey, “Low power wireless microphone
transceiver
based on analog to time conversion for cochlear implant application”, IEEE
Singapore Section Microwave Theory and Techniques/Antennas and
Propagation,
ECE NUS, Singapore, 2013.
G. Jacquemod, D.
Jausseran, O. Diop, Y. Vaiarello, A. El Amraoui, F. Ferrero, W.
Tatinian, A.
Diallo, Y. Leduc, N. Veau, C. Laporte, H. Ezzeddine & C. Luxey,
“Low power
wireless microphone transceiver based on analog to time conversion for
cochlear
implant application”, ICSS, Orlando, USA, pp. 74-82, 2012.
Y. Vaiarello, Y.
Leduc, N. Veau & G. Jacquemod, “Process variation compensation for
wireless
microphone applications”, VARI, Sophia Antipolis, France, 2012.
Y. Leduc, “Solutions
pour éliminer les derniers éléments passifs autour
des SoCs”, FETCH,
Alpe d'Huez, France, 2012.
Y. Leduc
& G. Jacquemod, “Comparison How to take
profit of 3D IC integration?”, D43D, Grenoble, France,
2011.
Y. Leduc & G.
Jacquemod, “Projet DAIKON : Microcontrôleur multicoeur
réalisé en technologie
asynchrone”, FETCH, Montréal, Canada, 2011.
Y. Leduc, “La 3eme
dimension peut-elle être le futur des systèmes
embarqués ?”, FETCH,
Chamonix, France, 2010.
Y. Leduc,
“Power and Energy Management”, ECOFAC,
Chexbres, 2010.
Y. Leduc, “Les
spécifications exécutables, une réponse
à la complexité de la conception
des systèmes hétérogènes”, FETCH,
Chexbres, 2009.
Conférences
internationales :
M. Moign,
J.-P. Leca, N.
Froidevaux, Y. Leduc & G.
Jacquemod, “Effect
of SSN on signal and power integrity on 32-bit microcontroler: Modeling
and correlation", PRIME,
Lausanne, Switzerland, pp. 193-196, 2019, Bronze Paper Award.
H. Jouni,
A. Harb, G. Jacquemod & Y. Leduc, “Creation
of real blocks for neural networkusing Simulink”, ICCA, Beirut, Lebanon, 2018.
Z.
Wei, G.
Jacquemod,
J. Prouvee, E.
de
Foucauld
& Y.
Leduc,
“Low
power IoT design using FDSOI technology”, SENSO, Gardanne,
France,
2017.
H. Jouni, A. Harb,
G. Jacquemod & Y. Leduc, “Programmable
signal generator for neural network application”, ICM,
Beirut,
Lebanon, 2017.
G.
Jacquemod, Z. Wei, Y. Leduc & E. de Foucauld, “Back-gate
cross-coupled
cells for high performance clock in 28nm FDSOI technology”, Nano-Science
&
Technologie, Fukuoka, Japan, 2017.
Z.
Wei, Y. Leduc, E. de Foucauld & G. Jacquemod, “Novel building blocks
for PLL using complementary
logic in 28nm UTBB-FDSOI technology”, NEWCAS, Strasbourg,
France, pp.
121-124, 2017.
H. Jouni,
A. Harb, G. Jacquemod & Y. Leduc, “Wide range analog CMOS multiplier for
neural
network application”, EEETEM, Beirut, Lebanon,
2017.
Z.
Wei, Y. Leduc, G. Jacquemod
& E. de Foucauld, “UTBB-FDSOI
complementary logic for
high quality analog signal processing”, ICECS, Monaco, pp.
572-575,
2016.
H. Jouni,
M. Issa, A. Harb, G. Jacquemod & Y.
Leduc, “Neural network
architecture for
breast cancer detection and classification”, IMCET, Beirut, Lebanon,
2016.
G.
Jacquemod, Z. Wei, Y. Leduc & C. Jacquemod, “New QVCO Design using UTBB FDSOI
technology”, EWME, Southampton, UK, 2016.
G. Jacquemod, Z.
Wei, P. Lorenzini & Y. Leduc, “New
Design using UTBB FDSOI technology”, CDNLive, Munich,
Germany,
2016
G. Jacquemod, Z.
Wei, J. Modad, E. de Foucauld, F. Hameau, Y. Leduc & P. Lorenzini, “Study and reduction of variability in
28nm FDSOI
technology”, VARI/PATMOS, Salvador Bahia, Brazil, 2015,
p. 19-22.
D. Jausseran, Y.
Vaiarello, A. El Amraoui, Y. Leduc, N. Veau & G. Jacquemod,
“Wireless
Microphone Receiver based on Analog to Time Conversion”, SAME,
Sophia
Antipolis, France, 2012
U. Cerasani, Y.
Vaiarello, Y. Leduc & G. Jacquemod, “Matlab/Simulink modeling of RF
microphone
for cochlear implant application”, SAME, Sophia Antipolis,
France, 2011.
Y.
Vaiarello, Y. Leduc, N. Veau & G. Jacquemod,
“Low power RF ADC based on voltage to time conversion”, SAME,
Sophia
Antipolis, France, 2011. Best Demo Award
Y.
Vaiarello, W. Tatinian, Y. Leduc, N. Veau & G.
Jacquemod, “Ultra low power transmitter for cochlear implant
application”, CAS-FEST,
Rio de Janeiro, Brazil, 2011.
Conférences
nationales
:
M. Moign,
J.-P. Leca, N. Froidevaux, G.
Jacquemod & Y. Leduc,
“Analyse,
modélisation et réduction du bruit de commutation
simultanée généré par les interfaces
d'Entrées/Sorties haute vitesse dans les mircocontrôleurs”, JNRDM, Montpellier, 2019.
Y. Leduc & N.
Messina, “Save
power, increase performances, insure functionality: Bypass your high
speed IC's”, RF & Microwave, Session "CEM
des circuits intégrés et des cables", Paris, 2019.
M. Moign,
J.-P. Leca, N. Froidevaux, G.
Jacquemod, H.
Braquet & Y. Leduc,
“Microcontrollers
Electromagnetic Interferences (EMI) modeling and reduction”, RF & Microwave, Session "CEM
des circuits intégrés et des cables", Paris, 2019.
