Titre
de la thèse : Etude
et développement
de transistors CMOS haute tension et de cellules mémoires
non-volatiles compatibles en technologique 28nm FDSOI
Directeur
de thèse : Pascal
Masson
Financement
: Convention Cifre STM Rousset
Domaine d'activité :
Mémoires
non-volatiles embarquées, transistors haute
et moyenne tension, 28FDSOI, process integration
Publications :
Conférences "invité" :
D.
Morillon, F. Julien, J. Delalleau, A.
Villaret, J.-C. Grenier, G. Ghezzi, F. Arnaud & S. Niel, “High
and
medium voltage devices integration on advanced eNVM”,
Leading Edge
Embedded NVM, Gardanne,
France,
2017.
Conférences
internationales :
D.
Morillon,
P. Masson, F. Julien, P. Lorenzini, J. Goy,
C. Pribat, O. Gourhant, T. Kempf, J.-L. Ogier, A. Villaret, G. Ghezzi,
N.
Cherault & S. Niel, “Gate Oxide Degradation Assessment by
Electrical Stress
and Capacitance Measurements,” International
Integrated Reliability Workshop, Fallen Leaf Lake, CA, USA, 2018.
D.
Morillon, C. Pribat, F. Julien, N. Cherault, J. Goy, O. Gourhant,
J.-L. Ogier, P. Masson, G. Ghezzi, T. Kempf, J. Delalleau, A. Villaret,
J.-C.
Grenier & S. Niel, “Study of HTO-based alternative gate oxides for
high
voltage transistors on advanced eNVM technology”,
International Integrated Reliability Workshop, Fallen Leaf Lake,
USA, 2017.
D.
Morillon, F. Julien, J. Coignus, A. Toffoli, L. Welter, C. Jahan,
J.-P. Reynard, E. Richard & P. Masson, “High
voltage MOSFETs integration on advanced CMOS technology:
Characterization of thick gate oxides incorporating high k metal gate
stack
from logic core process”, IEEE ICMTS, Grenoble,
France, 2017.
A.
Dobri, D. Morillon, S. Jeannot, F. Piazza, C. Jahan, A. Toffoli, L.
Perniola & F. Balestra, “Evaluation of ONO compatibility with
high-k metal
gate stacks for future embedded flash products”,
EUROSOI-ULIS, Athens, Greece, 2017.
Conférences
nationales :
D.
Morillon, F. Julien & P. Masson, “High
and
medium voltage transistors for embedded non-volatile memories on 28nm
FDSOI
technology”,
JNRDM, Strasbourg,
2017.
D.
Morillon, F. Julien & P. Masson, “Etude et développement de
transistors haute tension et de cellules mémoires non volatiles
en 28nm FDSOI”, JNRDM, Toulouse, France, 2016.
